1. Field of the Invention
This invention relates to a method for fabricating a capacitor, and more particularly, relates to a method for fabricating a DRAM cell and simultaneously increasing capacitance of the capacitor as well as reducing step height between the periphery circuit region and the memory cell region of the DRAM cell.
2. Description of the Prior Art
For high density DRAMs, such as in the 1 GB DRAM and larger, the density of the memory cells is increased when compared with the low capacity DRAMs. A DRAM cell contains a memory cell array region and a periphery region. The memory cells are formed within the memory cell array region, and the periphery circuit is fabricated in the periphery region. The memory cell in the memory cell array region is basically composed of a transistor and a capacitor, which includes a storage node as a cubic electrode of the capacitor. Due to the high intensity of memory cell, and the structure of the storage node, the step height between the memory cell array region and the periphery region introduces a serious problem, such as exposure, alignment, and focus, in following processes that fabricating the DRAM.
In order to increase the charges stored in a capacitor, a stacked capacitor is developed, but there is a difference between the altitude of the stacked capacitor in a memory cell region and the altitude of the periphery region. As shown in FIG. 1, the cross-sectional view of a wafer shows that a memory cell region 10 and a periphery region 11 are on a substrate 12. A first bit line 14 and a gate electrode 15 of a transistor are formed on the substrate 12, in addition, a first dielectric layer 16 is formed on and between the first bit line 14 and the gate electrode 15. Then a second bit line 20 and a third bit line 21 are formed on the cubic dielectric layer 16, besides, a second dielectric layer 23 is formed on the second bit line 20 and the third bit line 21. A third dielectric layer 24 is formed on topography of the wafer including the memory cell region 10 and the periphery region 11, in addition, the second dielectric layer 23 between the second bit line 20 and the third dielectric layer 24 acts as an diffusion barrier layer. During fabricating a storage node 25 of the capacitor in the memory cell region 10, the third dielectric layer 24 is etched and a first dielectric material is formed on the etched on the third dielectric layer 24. The storage node 25 made of the first conductive material is a first electrode of the capacitor.
To fabricate an insulating film of the capacitor, the third dielectric layer 24 is partially removed to expose a cubic portion of the storage node. Refer to FIG. 2, the fourth dielectric layer 30 is formed on the exposed storage node 25 and on the etched third dielectric layer 24, subsequently, a conductive layer 31 is formed on the fourth dielectric layer 30. Then the fourth dielectric layer 30 and the conductive layer 31 are patterned to fit the necessary size. The patterned fourth dielectric layer 30 and the conductive layer 31 act as the insulating layer and the second conductive plate of the capacitor respectively. Thus the transistor is fabricated in the memory cell region 10. To isolate the electricity of the capacitor composed of the fourth dielectric layer 30, the conductive layer 31 and the underlying storage node 25, a fifth dielectric layer 35 is formed on the topography of the wafer including the memory cell region 10 and the periphery region 11.
After the capacitor is fabricated, proceed with the periphery region 11 to manufacture the periphery circuit in the periphery region 11. So the periphery circuit mentioned above, the bit lines and the gate electrode 15 of the transistor are formed as shown in FIG. 3. In addition, the periphery circuit mentioned above, the bit lines and the gate electrode 15 of the transistor are used to control the charge stored in the stacked capacitor. Due to the exposed portion of the stacked capacitor, as shown in FIG. 3, the altitude of the fifth dielectric layer 35 in the memory cell region 10 is higher than the altitude of the fifth dielectric layer 35 in the periphery region 11. The altitude difference .alpha. between the memory cell region 10 and the periphery region 11 of the prior art DRAM shown in FIG. 3 is the step height between the memory cell region 10 and the periphery region 11. Due to the step height .alpha., it is difficult to proceed with the periphery region 11 to form the periphery circuit in the periphery region 11 because of the problems such as focus problem raised from the step height .alpha..